1. Field of the Invention
The present invention relates to an electronic device, in particular, to an electronic device of which a semiconductor package is mounted on a wiring substrate as a mother board with high reliability. In addition, the present invention relates to a semiconductor package, in particular, to a semiconductor package that is mounted on a wiring substrate as a mother board with high reliability.
2. Description of the Related Art
To decrease the size of an electronic device and compact circuit structure thereof, a semiconductor element (for example, an IC chip) is mounted on a multi-layered wiring substrate composed of ceramics or the like. The mounted area is sealed with a metal cap or molding resin.
Particularly, in a semiconductor element such as a CPU that consumes a high power, a heat sink is disposed so as to give off heat from the element.
In addition, to reduce the cost of the fabrication of an electronic device and simplify the structure thereof, a TCP (tape carrier package) has been used. In the TCP, a semiconductor element is mounted on a carrier tape that has wirings such as inner leads. A shape-holding plate (referred to as stiffener) is disposed on the semiconductor element. In addition, a heat radiating cover is disposed on the stiffener. To allow the number of input/output terminals to be increased, the outer size to be decreased, and a semiconductor device to be easily mounted, solder balls or the like are disposed in a grid pattern on connecting pads that are external connecting terminals. This structure is referred to as ball grid array (BGA).
FIG. 4 is a perspective view showing an example of the structure of conventional tape-BGA type semiconductor package. In FIG. 4, reference numeral 1 is an insulating resin film having a device hall. An example of the insulating resin film 1 is a polyimide film. Reference numeral 2 is an inner lead disposed on one main face (for example, on the lower surface) of the insulating resin film 1. The inner lead 2 protrudes to a device hole. Many inner leads 2 are disposed corresponding to electrode pads of a semiconductor element. Wiring (not shown) such as signal lines is connected to the rear end of the inner leads 2. Connecting pads (not shown) as external connecting terminals are disposed on the edges of the relevant wirings. Reference numeral 3 is a semiconductor element disposed with face down in a device hole. Each electrode pads of the semiconductor element 3 are electrically connected to the edges of the relevant inner leads 2. Reference numeral 4 is a resin sealing layer that coats and seals a connecting area of the semiconductor element 3. Reference numeral 5 is a bump composed of for example a solder ball. Solder bumps 5 are disposed on the relevant connecting pads. Reference numeral 6 is a frame shape-holding plate (stiffener) adhered to the other main face (for example, the upper face in FIG. 4) of the insulating resin film 1 with an adhesive agent 7. Reference numeral 8 is a cover plate disposed on the other face of the stiffener 6 and the semiconductor element 3. The cover plate 8 has heat radiating characteristic and is adhered with an adhesive agent 9.
This semiconductor package is mounted on a wiring substrate of the host (mother board) and thereby an electronic device is structured. In other words, connecting pads are disposed on one main face of the mother board corresponding to external connecting terminals (connecting pads) of the semiconductor package. The connecting pads of the mother board and the external connecting terminals of the semiconductor package are connected with bumps such as solder balls 5.
However, in an electronic device with a semiconductor package, a stress due to a thermal load that is applied in fabrication process or in operation concentrates at the solder balls 5 that connect the external connecting terminals of the semiconductor package and the connecting pads of the mother board and thereby the semiconductor package warps.
In other words, as a mother board, a glass-epoxy wiring substrate of which glass cloths impregnated with epoxy resin and copper wiring layers are laminated is usually used. The average thermal expansion coefficient (TEC) of the wiring substrate is in the range from 13.times.10.sup.-6 to 18.times.10.sup.-6 /.degree.C. (/K) although it varies depending on the wiring density and the wiring direction.
On the other hand, since the stiffener 6 whose thickness is the largest in the semiconductor package shown in FIG. 4 (in other words, the stiffener 6 mainly affects TEC of the semiconductor package) is usually composed of stainless steel (for example, SUS 304 whose TEC is 17.3.times.10.sup.-6), there is an inconsistency in physical property values between the semiconductor package and the mother board.
When the difference of the physical characteristics is large, since the outer lead portion of the QFP (Quad Flat Package) formed in a gull wing shape elastically deforms, it absorbs and relieves the distortion due to the concentrated stress. On the other hand, since the BGA type semiconductor package does not have a portion that absorbs and relieves such a distortion, the periodic temperature change causes the bumps such as solder balls 5 that connect the semiconductor package and the mother board to be repeatedly stressed. Thereby, the bumps are fatigued and broken.
FIG. 5 shows the structure of an electronic device of which a QFP is mounted on a glass-epoxy wiring substrate. Referring to FIG. 5, reference numeral 10 is a bed portion of a lead frame. 11a is an inner lead portion, and 11b is an outer lead portion. 12 is an semiconductor element, and 13 is a bonding wire that connects an electrode terminal (not shown) of the semiconductor element and the inner lead portion 11a. 14 is molding resin composed of epoxy resin, and 15 is a glass-epoxy wiring substrate as a mother board. 16 is a solder fillet that connects the outer lead portion 11b of the QFP to a predetermined wiring portion (not shown) of the glass-epoxy wiring substrate 15.